FIG. 1 illustrates a schematic block diagram of a computer system. As shown, the computer system includes a central processing unit (CPU) 1000 operably coupled to local cache 1002 and to a north bridge 1004. The central processing unit 1000 when executing a memory transaction (e.g., a read from memory command, a write to memory command, or a read/write command) internally processes addresses associated with the transaction in virtual, or linear, address space. To communicate with the north bridge, the central processing unit converts the virtual addresses into physical addresses. The north bridge, upon receiving the physical addresses, determines whether the transaction is addressing a location within a DRAM address space, or a PCI address space.
If the received physical address corresponds to the GART address space, the north bridge 1004 may further translate the physical address, using a GART table, into a corresponding physical address. Having obtained the physical address, the north bridge 1004 communicates with a memory 1006 to retrieve an appropriate memory block (e.g., line of memory, or multiple lines of memory where a line is 32 bits, 64 bits, 128 bits, etc.). If the physical address corresponds to the memory 1006, the north bridge 1004 utilizes the physical address to facilitate the memory transaction. As such, if the memory transaction was a read transaction, the north bridge 1004 facilitates the retrieval of the corresponding memory line or lines from memory 1006 and provides them to the central processing unit 1000. If the received physical address corresponds with the PCI address space, the north bridge 1004 passes the transaction to the PCI bus 1008.
The south bridge 1010, upon receiving a physical address, determines which of the plurality of I/O devices 1012, 1014, 1016 is to receive the transaction.
In addition to the north bridge 1004 receiving transactions from the central processing unit 1000, it may also receive transactions from a video graphics processor 1020 and the south bridge 1010 relaying transactions from I/O devices 1012, 1014, 1016. Such transactions have varying requirements. For example, transactions from the central processing unit 1000 and video graphics processor 1020 are typically high speed transactions which require low latency. The amount of data in such transactions may vary but is generally a memory line or plurality of memory lines per transaction. The transactions from the I/O devices 1012, 1014, 1016 are generally large amounts of data (i.e., significantly more than several memory lines of data), but are typically latency tolerant.
The video graphics processor 1020 provides display data to a display (not shown). Typically, the video graphics processor 1020 will include a frame buffer for storing at least part of a screen's worth of data. To minimize the size of the frame buffer or to extend the memory used for generating the display data, the video graphics processor 1020 often uses system memory. Sometimes these processes are inside the AGP aperture. In this instance, the video graphics processor 1020 is writing to and reading from the memory 1006 via the AGP 1022 bus and the north bridge 1004. The processing of video graphics data requires a high speed low-latency transmission path.
As is known in the prior art, upon initialization of the system, each application specific integrated circuit (ASIC), such as the graphics processor 1020, has base address registers which define the starting address of a program, table, memory structure, set of registers etc. An ASIC is a chip that is custom designed for a specific application rather than a general purpose chip, such as a microprocessor. The use of ASICs improves performance over general purpose CPUs, because ASICs are hard wired to do a specific task and do not include the overhead of fetching and interpreting stored instructions. There are many varieties of ASICs.
In order to determine the system configuration upon initialization, the computer system reads queries the system components to determine which resources are required. For example, some components have address ranges that they would like to have mapped into system's address spaces. In PCI systems, this information is communicated via base address registers (BARs). In the prior, art this has been accomplished by the use of a limited number of straps or in PC's is most commonly configured using BIOS routines and specialized hardware in each ASIC to support these routines.
It is a drawback of the prior art that each of the approaches for reading the base address registers upon initialization is limited. The AGP bus is only defined to support one AGP master device. This is a further drawback in the prior art since it is desirable to use more than one AGP master device in some systems.
Consequently, a need exists for an improved method and apparatus for interfacing ASIC's to a system and a more versatile register configuration mechanism.